fpga-development

About this Skill

Design, review, simulate, and verify FPGA logic using explicit RTL contracts, clock and reset models, CDC analysis, timing constraints, and reproducible implementation evidence. Use for synthesizable HDL, fixed-point arithmetic, handshakes, testbenches, resource tradeoffs, timing closure, and FPGA release or bring-up planning. Do not use for ordinary MCU firmware, generic circuit design, a substitute vendor-tool manual, or unsupported claims of hardware or timing signoff.

Cas d’usage

• Design synthesizable RTL and fixed-point arithmetic
• Review clock, reset, and CDC behavior
• Create self-checking simulation plans and testbenches
• Analyze timing constraints and implementation tradeoffs
• Prepare FPGA release and hardware bring-up evidence

Fonctionnalités

• Explicit RTL, interface, clock, and reset contracts
• Guidance for simulation, scoreboards, and mutation checks
• CDC, timing constraint, and resource tradeoff reviews
• Release evidence tracking for source, tools, devices, and artifacts
• SystemVerilog ready/valid buffer and testbench fixture

Prérequis

• Python 3
• Icarus Verilog
• Yosys

Agents compatibles

Skill files

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